The present disclosure relates to the fabrication of metal oxide semiconductor field effect transistor (MOSFET) devices, and in particular to a method of fabricating dual gate MOSFET devices.
Over the past twenty-five years or so, the primary challenge of very large scale integration (VLSI) has been the integration of an ever-increasing number of MOSFET devices with high yield and reliability. This was achieved mainly by scaling down MOSFET channel lengths without excessive short-channel effects. Short-channel effects are the decrease in threshold voltage (Vt) in short-channel devices due to two-dimensional electrostatic charge sharing between the gate and the source/drain regions. Prior attempts to improve short-channel effects include forming retrograded wells by implanting a high concentration of counter-dopant at the channel and source/drain extensions. The high concentration of counter-dopant at the PN junctions (source/channel interface, channel/drain interface) of the device disadvantageously result in increased device leakage. Double-gated MOSFETs and MOSFETs with a top gate and a backside ground plane are more immune to short-channel effects than single gate MOSFETs to short-channel effects.